1. Field of the Invention
The present invention relates to an MIS (MOS) capacitor for an integrated circuit and, more particularly, to an MIS (MOS) capacitor for a bipolar integrated circuit.
2. Description of the Related Art
An MIS (MOS) capacitor has been utilized as a part of a bipolar IC or a MOS IC which is monolithically formed in a semiconductor substrate, e.g., a silicon substrate. An MIS capacitor formed in a bipolar IC will be described below with reference to FIG. 1.
After an N.sup.- -type island region 2 having an N.sup.+ -type buried region 3 is formed in a P-type semiconductor substrate 1, an N.sup.+ -type semiconductor layer 4 is provided in the N.sup.- -type island region 2, and a first metal electrode 7 is provided on a thin insulating layer 5 formed on the N.sup.+ -type semiconductor layer 4. A second metal electrode 8 is provided on the N.sup.+ -type semiconductor layer 4 through an opening formed in a thick insulating layer 6 such as a field insulating layer, thereby providing an MIS capacitor 9.
As shown in FIG. 4, a capacitance C14 of the MIS capacitor 9 is provided by a capacitance Cox10 of the insulating layer 5 and a capacitance Csll of the surface of the semiconductor layer 4 connected in series with each other. In this case, the capacitance Csll includes a capacitance Cdep 12 and a capacitance Cinv 13 which are connected in parallel with each other. The capacitance Cdep 12 is provided by impurity ions (donor ions in the case of N-type ions), while the capacitance Cinv 13 is provided by a carrier stored at a surface of the semiconductor layer 4. Although the capacitance Cox10 is constant without depending upon a bias voltage, the capacitance Csll depends on the bias voltage. In the structure, the MIS capacitor 9 is designed in such a manner that the depletion layer does not easily extend by increasing the impurity concentration of the semiconductor layer 4 (the capacitance Csll is sufficiently higher than the capacitance Cox10), and the capacitance C14 does not depend on the bias voltage as a whole.
As a method of making an insulating layer, chemical vapor deposition techniques as well as thermal oxidation techniques have been known. As a thin insulating layer, a silicon oxide film, a nitride film, a tantalum nitride film, or the like are given. As an electrode metal layer, polysilicon having good electric conductivity can be utilized in addition to metals such as aluminum.
In a conventional MIS capacitor, in order to reduce an unwanted resistance, a process for increasing the impurity concentration of the semiconductor layer is required as described above. On the contrary, if the impurity concentration is decreased, the capacitance of the capacitor depends on a bias voltage, and drawbacks to be described later may occur. In addition, when the capacitance Cox10 is increased by further decreasing the thickness of the thin insulating layer 5 so as to improve a capacitance per unit area, the impurity concentration of the semiconductor layer 4 must be increased. Therefore, crystal defects may occur in the semiconductor layer 4.
In general, a capacitor having the MIS (MOS) structure (an N-type semiconductor layer is used as a semiconductor layer for descriptive convenience) is given by the capacitance C14 which is provided by the capacitance Cox10 and the depletion layer capacitance Csll connected in series with each other as shown in FIG. 4. The capacitance Cox10 is defined by the dielectric constant of the thin insulating layer, its thickness, and its area, and the depletion layer capacitance Csll is defined by the dielectric constant of silicon, the width of depletion layer, and the inverted carrier distribution. In addition, the capacitance Csll is given by the capacitance Cdep12, caused by donor impurity ions, and the capacitance Cinv13, caused by the inverted carriers generated on the surface of the semiconductor layer 4.
In the MIS capacitor having the above structure, a positive voltage is applied to a first electrode 7 while a negative voltage is applied to a second electrode 8, i.e., the semiconductor layer 4. In such a forward bias condition, electrons of majority carriers are stored in the surface of the semiconductor layer 4 located below the insulating layer 5 as indicated by reference numeral 15 in FIG. 2A. In this state, since the capacitance Csll becomes very high, the capacitance C14 is approximately equal to the capacitance Cox10.
On the contrary, when a negative voltage is applied to the first electrode (reverse bias), as shown in FIG. 2C, holes of minority carriers are generated on the surface of the semiconductor layer 4 by the negative potential, thereby providing an inversion layer 16 therein. At this time, even if the voltage applied to the first electrode includes a DC bias or AC signal components, the capacitance Cinv13 is increased when the voltage is a low frequency. Accordingly, the capacitance C14 is approximately equal to the capacitance Cox10. However, if the reverse bias voltage includes high frequency components, a generation recombination rate of inversion carriers cannot follow a change in the high frequency components. Therefore, the capacitance Cinv13 is decreased, thereby decreasing the capacitance C14 of the capacitor.
When the first electrode 7 is in a zero bias state or the forward bias state is changed to the reverse bias state, electrons are excluded from the surface of the semiconductor layer 4 by the negative potential, thereby providing a depletion state 17 as shown in FIG. 2B. This state is called a deep depletion state. When a very high voltage is applied to the semiconductor layer 4, the capacitance C14 of the capacitor is decreased until breakdown occurs in the depletion layer. Few inversion carriers which are described above are present in this state.
It may be considered that since holes of the inversion carriers in the MIS structure using the N-type semiconductor are recombined with electrons from the positive electrode to the semiconductor surface, few holes reach the semiconductor surface, and a great number of holes are produced by electrons holes pairs. At this time, the electrons hole pairs are produced by light excitation if light is applied to the semiconductor layer. If crystal defects are formed in the semiconductor layer, they may serve as centers for generating electrons hole pairs. Accordingly, if the crystallinity of the semiconductor layer 4 is improved so as to obtain good characteristics of the capacitor, holes may not be easily produced.
FIG. 3 shows a relationship between an applied voltage vg to the capacitor (assuming that the semiconductor layer 4 is kept at a ground potential and the voltage Vg is applied to the first electrode 7) and the capacitance C14 of the capacitor. In the drawing, a solid line represents a high frequency response characteristic (about 100 Hz or more); a broken line, a low frequency response characteristic; an alternate long and short dashed line, a characteristic of a deep depletion layer; and Cox, a capacitance of the insulating layer 5 itself, respectively.
When the capacitor is operated under the DC state, it has the characteristic represented by the broken line in FIG. 3. Since the semiconductor surface becomes the inverted state even when the capacitor is biased in the reverse direction (negative bias), the capacitance of the capacitor has the same value as that when the capacitor is biased in the forward direction. When the reverse bias having the high-frequency components is applied to the capacitor, the characteristics represented by the solid line in FIG. 3 can be obtained, whereby the capacitance indicates the frequency dependence. When the capacitor is switched at a high speed or a surge voltage is applied to the capacitance, i.e., when an applied voltage is rapidly raised from a zero bias state, the capacitor becomes the deep depletion state. At this time, the capacitance C14 is further decreased so as to have a value represented by an alternate long and short dashed line in FIG. 3.
As described above, the actual capacitance C14 of the capacitor is different from a designed capacitance value of a semiconductor element except that the DC bias voltage is applied to the capacitor. In addition, since a decrease in the capacitance C14 of the capacitor means a decrease in energy accumulated in the capacitor, the capacitor may be broken when a high surge voltage is applied thereto.
As described above, in the conventional technique, since the capacitor is designed such that the impurity concentration of the semiconductor layer 4 is increased so as not to easily extend the the depletion layer (the capacitance Csll is increased), the capacitance is rarely decreased even in the depletion state. However, when the impurity concentration is decreased due to variations in the steps of making the capacitor, the capacitance C14 of the capacitor is decreased. Therefore, the yield of capacitors may be reduced due to degradation of the high frequency characteristic and the breakdown by the surge voltage.